Layout design on bond pads to improve the firmness of bond wire in packaged IC products

Author

Peng, Jeng-Jie ; Ker, Ming-Dou ; Wang, Nien-Ming ; Jiang, Hsin-Chin

Author_Institution

VLSI Design Div., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

1999

fDate

1999

Firstpage

147

Lastpage

150

Abstract

During the manufacture of IC products, the breaking of bond wires or the peeling of bond pads occurs frequently and thus results in the open circuit phenomenon in the IC´s. There are several methods proposed to overcome this problem, but additional special process flows are desired for all of these previous methods. This paper presents a layout design method to improve the bond wire reliability in a standard CMOS process. By changing the layout patterns on the bond pads, the firmness of bond wires on the bond pads can be improved. One set of layout patterns on the bond pads has been designed and fabricated in a 0.6 μm IP3M CMOS process for the ball shear test and the wire pull test. By implementing the effective layout designs in IC products, the bond wire reliability can be obviously improved in a standard CMOS process

Keywords

CMOS integrated circuits; integrated circuit layout; integrated circuit packaging; integrated circuit reliability; lead bonding; 0.6 micron; IP3M CMOS process; ball shear test; bond pad layout patterns; bond wire reliability; layout design method; packaged IC products; standard CMOS process; wire pull test; Atherosclerosis; Bonding; CMOS process; Design methodology; Dielectric materials; Inorganic materials; Integrated circuit layout; Integrated circuit packaging; Testing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.786022

Filename

786022