The VLSI Design of Winscale for Digital Image Scaling

The resolution of digital displays has been improved with increment of the display sizes of those devices. The digital image scaling algorithm, winscale, is suitable for digital display devices in various resolutions; nevertheless, the computational complexity of winscale algorithm is not able to process in real-time. In this paper, we implement an efficient VLSI architecture design of winscale algorithm. The core consists of coordinate accumulator, pixel orientation unit, area calculation unit, and multiplication-addition unit. Base on our technique, the high speed VLSI architecture has been successfully designed and implemented. The simulation results demonstrate that the high performance architecture of image scaling at 130.24 MHz with 17414 gates in a 450 x 450 mum core area of chip is able to process digital image scaling for HDTV in real-time.