Improving efficiency in a Batcher-banyan packet switch

A broadband packet switch adopting a Batcher-banyan interconnection network is described. Using dedicated hardware, contention between input port controllers for the output ports is solved before transmitting the user packets. No complex design is required for this hardware; as it basically uses chips already required in a Batcher-banyan packet switches, several contention cycles can be run without requiring internal clocks incompatible with the available technology. This feature permits service policies of the input queues in this switch other than FCFS. A reduction of the head-of-line blocking typical of FCFS-input queued switches is obtained and, consequently, the throughput and delay performance of the switch is improved