An embedded march algorithm test pattern generator for memory testing

Author

Wang, Wei-Lun ; Lee, Kuen-Jong ; Wang, Jhing-Fa

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1999

fDate

1999

Firstpage

211

Lastpage

214

Abstract

The memory cores are essential for a system-on-a-chip (SOC). To test the memory cores, in this paper we propose a generalized embedded test pattern generator for any march algorithm. Without loss of functionality of the march algorithm, we also present a systematic procedure with a short time complexity to reduce the hardware cost of the test pattern generator

Keywords

VLSI; automatic test pattern generation; built-in self test; computational complexity; integrated circuit testing; integrated memory circuits; BIST; embedded test pattern generator; hardware cost reduction; march algorithm; memory cores; memory testing; short time complexity; system-on-a-chip; Built-in self-test; Circuit faults; Circuit testing; Costs; Coupling circuits; Fault detection; Hardware; Random access memory; System-on-a-chip; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.786037

Filename

786037

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3067086