DocumentCode :
3067140
Title :
Fault detection and location of dynamic reconfigurable FPGAs
Author :
Wu, Chi-Feng ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear :
1999
fDate :
1999
Firstpage :
215
Lastpage :
218
Abstract :
Dynamic reconfigurable FPGAs provide a platform for reconfigurable computing as well as fast prototyping and emulation. For such FPGAs, we propose a dynamic serial (DS) test approach which takes advantage of their dynamic reconfiguration feature for testing. Compared with the parallel approach, the DS test approach significantly reduces the test configuration time and requires less I/O pins, resulting in a faster and easier testing procedure for dynamic reconfigurable FPGAs
Keywords :
fault location; field programmable gate arrays; integrated circuit testing; logic testing; dynamic reconfigurable FPGAs; dynamic serial test approach; emulation; fast prototyping; fault detection; fault location; parallel testing; reconfigurable computing; test configuration time reduction; Circuit testing; Computer architecture; Emulation; Fault detection; Field programmable gate arrays; Hardware; Integrated circuit interconnections; Manufacturing; Prototypes; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location :
Taipei
ISSN :
1524-766X
Print_ISBN :
0-7803-5620-9
Type :
conf
DOI :
10.1109/VTSA.1999.786038
Filename :
786038
Link To Document :
بازگشت