Low-power multirate IF digital frequency down converter

Author

Jou, Shyh-Jye ; Wu, Shou-Yang ; Wang, Chorng-Kuang

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

fYear

1999

fDate

1999

Firstpage

231

Lastpage

234

Abstract

The architectural design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on a multirate algorithm. It can have very low-power dissipation owing to the reduction in hardware complexity and operational frequency. Design application for an IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6 mW when operated at 2 V

Keywords

CMOS digital integrated circuits; FIR filters; cellular radio; circuit complexity; code division multiple access; frequency convertors; integrated circuit layout; interpolation; low-power electronics; mixers (circuits); 0.6 mW; 2 V; 20 MHz; 4.9152 MHz; C²MOS latches; IF frequency; IF oversampling; IS-95 CDMA; architectural design; digital cellular telephony; hardware complexity; low-power dissipation; low-power multirate IF digital frequency down converter; mixers; multirate algorithm; multistage interpolated finite impulse response filter design; operational frequency; single-poly double-metal CMOS technology; Baseband; Digital filters; Digital-to-frequency converters; Finite impulse response filter; Frequency conversion; Hardware; Low pass filters; Multiaccess communication; Receivers; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.786042

Filename

786042