Author :
Koike, H. ; Takato, H. ; Hiyama, K. ; Yoshida, S. ; Harakawa, H. ; Kokubun, K. ; Shimabukuro, T. ; Kato, S. ; Tamaoki, M. ; Okano, H. ; Sato, H. ; Morimasa, Y. ; Yamamoto, T. ; Tanaka, M. ; Kumagai, J. ; Yakabe, O. ; Naruse, H. ; Kamijo, H. ; Tomioka, K.
Author_Institution :
Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan
Abstract :
This paper demonstrates a process integration for high performance and small footprint embedded DRAMs. A trench capacitor cell and a self-aligned bit line contact are selected to maintain exactly the same size as commodity DRAM cells. The cell array region is covered with a thin SiN barrier against salicidation. Ti-salicide source/drain is used in the logic region. No retention time degradation and good circuit performance are confirmed
Keywords :
CMOS memory circuits; DRAM chips; cellular arrays; embedded systems; logic design; memory architecture; 0.25 mum; 8 Mbit; SiN; Ti-salicide source/drain; TiSi2; cell array region; circuit performance; commodity DRAM cells; high performance logic; integrated embedded DRAM technologies; n-MOSFET; p-MOSFET; process integration; retention time degradation; salicidation; self-aligned bit line contact; small footprint embedded DRAMs; system-on-a-chip; thin SiN barrier; trench capacitor cell; Annealing; Capacitors; Costs; Electrodes; Logic arrays; Logic circuits; Plasma temperature; Random access memory; Silicon compounds; Switches;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
