Title :
Array pass transistor design in trench cell for Gbit DRAM and beyond
Author :
Li, Y. ; Mandelman, J. ; Parries, P. ; Matsubara, Y. ; Ye, Q. ; Rengarajan, R. ; Alsmeier, J. ; Flietner, B. ; Wheeler, D. ; Akatsu, H. ; Divakaruni, R. ; Mohler, R. ; Sunouchi, K. ; Bronner, G. ; Chen, T.C.
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
Abstract :
Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engineering, along with considerations of minimizing the junction leakage. By utilizing a 512 k array diagnostic monitor, a methodology is presented for optimum array cell design in a statistically reliable manner. Design issues unique to the trench capacitor cell are covered. Alternative biasing schemes that boost the process window are also discussed
Keywords :
CMOS memory circuits; DRAM chips; MOSFET; cellular arrays; leakage currents; memory architecture; 0.2 mum; DRAM cell size scaling; Gbit DRAM; array MOSFET; array pass transistor design; biasing schemes; channel length; channel width; diagnostic monitor; junction leakage minimization; leakage current requirement; optimum array cell design; process window; source/drain engineering; statistically reliable manner; trench capacitor cell; trench cell; Capacitors; Circuit testing; Data engineering; Implants; Leakage current; MOSFET circuits; Monitoring; Random access memory; Scalability; Threshold voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5620-9
DOI :
10.1109/VTSA.1999.786047
