Gate prespacers for high density DRAMs

Author

Divakaruni, R. ; Weybright, M. ; Li, Y. ; Gruening, U. ; Mandelman, J. ; Gambino, J. ; Alsmeier, J. ; Bronner, G.

Author_Institution

IBM Semicond. R&D Center, Hopewell Junction, NY, USA

fYear

1999

fDate

1999

Firstpage

255

Lastpage

257

Abstract

The channel length of the DRAM transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device. There is thus a need for novel integration schemes that allow the continued cell shrinkage with only limited shrinking of the channel length. In this paper, we present an integration scheme which allows for a larger gate polysilicon length for a given pitch thus improving array device leakage (by about one generation) for a given technology

Keywords

CMOS memory circuits; DRAM chips; cellular arrays; leakage currents; semiconductor technology; 200 nm; BEST cell; DRAM transfer gate device; Si-SiO₂; SiN; TEOS spacers; WSi; array device leakage; cell shrinkage; channel length; gate polysilicon length; gate prespacers; high density DRAMs; integration schemes; low leakage DRAM transfer device; pitch; scaling techniques; Annealing; Conductors; Doping; Etching; Implants; Oxidation; Random access memory; Resists; Silicon compounds; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.786048

Filename

786048