Title :
Hysteresis in floating-body PD/SOI CMOS circuits
Author :
Pelella, M.M. ; Chuang, C.T. ; Tretz, C. ; Curran, B.W. ; Rosenfield, M.G.
Author_Institution :
LOA, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) partially depleted (PD) SOI CMOS circuits is investigated. The change in gate propagation delay with time is examined with no preconditioning of the floating-body. The simulation-based analysis includes the sensitivity of the hysteresis to supply voltage, Wp/Wn (beta ratio), duty cycle, slew rate, output load, and initial state of the circuit. Basic physical mechanisms underlying the hysteretic circuit behavior are examined. The results identify the main contributors and general trends of hysteresis in FB PD/SOI circuits. The insight gained can ultimately be incorporated into conventional circuit timing tools. The results also reveal a circuit sizing methodology to minimize the hysteresis effects in circuits using PD/SOI technology
Keywords :
CMOS logic circuits; SPICE; circuit simulation; delays; hysteresis; integrated circuit modelling; silicon-on-insulator; timing; PD/SOI technology; SPICE model; beta ratio; circuit sizing methodology; circuit timing tools; duty cycle; floating-body partially depleted SOI CMOS circuits; history-dependent propagation gate delay; hysteresis effects minimization; hysteretic circuit behavior; hysteretic propagation gate delay; initial state; output load; physical mechanisms; simulation-based analysis; slew rate; static CMOS inverter; supply voltage; CMOS logic circuits; CMOS technology; Circuit simulation; Hysteresis; MOS devices; Predictive models; Propagation delay; Pulse width modulation inverters; Semiconductor device modeling; Voltage;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5620-9
DOI :
10.1109/VTSA.1999.786054
