The conversion of bulk CMOS circuits to SOI technology and its noise impact

Author

Wang, Li-kong ; Chen, Howard H.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1999

fDate

1999

Firstpage

282

Lastpage

285

Abstract

The faster switching speed and smaller parasitic capacitance of SOI circuits have provided 20% performance improvement over their bulk predecessors, but the characteristics of SOI circuits also introduced significant noise problems that cannot be overlooked. This paper addresses the design issues of remapping bulk CMOS circuits to the SOI technology, and discusses how to minimize the power supply noise by optimizing the placement of on-chip decoupling capacitors

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; integrated circuit layout; integrated circuit noise; silicon-on-insulator; SOI CMOS circuit conversion; bulk CMOS circuit remapping; bulk technology; design issues; distributed switching circuit model; full-chip noise analysis; hierarchical power bus model; noise impact; on-chip decoupling capacitors; parasitic capacitance; performance improvement; placement optimization; power supply noise; switching speed; CMOS technology; Capacitors; Circuit noise; Crosstalk; Design optimization; Parasitic capacitance; Power supplies; Silicon on insulator technology; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.786055

Filename

786055