A multichannel input subsystem

A large amount of technical literature describing digital filter implementations has been aimed at approaches that have utilized fully custom VLSI chip designs or semi-custom designs using commercial DSP chip sets. This paper describes a high performance, multichannel analog acquisition subsystem that utilizes a common timing-control structure to drive multiple digital filters that are implemented with standard TTL components. The digital filter operates at a 262 kHz sample rate, has a passband ripple of ±.08 dB, stopband attenuation of greater than 80 dB and is constructed with only 36 IC´s. The filter uses a technique that needs no hardware multipliers known as the Peled-Liu ROM-ACCUMULATOR architecture [1].