A 120 MHz BiCMOS superscalar RISC processor

Author

Tanaka, S. ; Hotta, T. ; Murabayashi, F. ; Iwamura, M. ; Yamada, H. ; Katsura, K. ; Ikeda, K. ; Matsuo, T. ; Takemoto, T. ; Matsubara, K. ; Kume, M. ; Saitou, K. ; Nakano, T. ; Mori, K. ; Shimizu, T. ; Satomura, R. ; Kitamura, N. ; Hayashi, T. ; Doi, T. ;

Author_Institution

Res. Lab., Hitachi Ltd., Ibaraki, Japan

fYear

1993

fDate

19-21 May 1993

Firstpage

9

Lastpage

10

Abstract

Several techniques such as BiCMOS, RISC, and superscalar have been developed to increase microprocessor performance. In the superscalar processor, multiple instructions should be fetched from the instruction cache and issued to the execution unit every machine cycle. However, due to the complex logic that is necessary for multiple issuing of instructions, the resulting machine cycle time tends to be relatively long. Consequently, the tradeoffs between clock rate and superscalar complexity should be carefully examined. In this paper, we describe a superscalar RISC processor which attains high operation speed.

Keywords

BiCMOS integrated circuits; digital arithmetic; microprocessor chips; pipeline processing; reduced instruction set computing; 120 MHz; BiCMOS; clock rate; execution unit; instruction cache; microprocessor performance; multiple instructions; multiple issuing; operation speed; superscalar RISC processor; BiCMOS integrated circuits; Integrated circuit design; Microprocessors; Pipeline arithmetic;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920514

Filename

920514