Title :
A fuzzy logic inference processor
Author :
Fattaruso, J. ; Mahant-Shetti, S.S. ; Barton, J.B.
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
This mixed analog-digital fuzzy logic inference processor chip calculates the result of an inference over a 32-rule knowledge base in parallel. Simulations predict a computation time for the array of about 2 /spl mu/sec. The processor interface behaves like a static RAM, but internal computation is performed in the analog domain to an expected precision of 6 bits. The completed chip measures 7 mm by 10 mm in a 0.8 /spl mu/m CMOS technology, and is currently undergoing preliminary testing.
Keywords :
CMOS integrated circuits; VLSI; fuzzy logic; inference mechanisms; microprocessor chips; mixed analogue-digital integrated circuits; parallel architectures; uncertainty handling; 0.8 micron; 32-rule knowledge base; CMOS technology; fuzzy logic inference processor; mixed analog-digital processor chip; parallel processing; Application-specific integrated circuits; CMOS integrated circuits; Fuzzy logic; Inference mechanisms; Microprocessors; Parallel architectures; Very-large-scale integration;
Conference_Titel :
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIC.1993.920526
