DocumentCode
3069214
Title
A charge recycle refresh for Gb-scale DRAMs in file applications
Author
Kawahara, T. ; Horiguchi, M. ; Kawajiri, Y. ; Akiba, T. ; Kitsukawa, G. ; Kure, T. ; Aoki, M.
Author_Institution
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
fYear
1993
fDate
19-21 May 1993
Firstpage
41
Lastpage
42
Abstract
A low-power charge recycle refresh featuring alternative operation of two arrays was proposed. After amplification in the first array, the charges in that array are transferred to the other array, where they are recycled for half the amplification there. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is also reduced. This technique can reduce the data retention current in Gb-scale or subGb-scale DRAMs, where the reduction of data-retention current by extending the refresh period is limited by the cell retention time.
Keywords
DRAM chips; VLSI; amplification; Gbit-scale DRAMs; charge recycle refresh; data retention current; data-line current dissipation; dynamic RAM; file applications; low-power refresh; voltage bounce reduction; DRAM chips; Very-large-scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location
Kyoto, Japan
Type
conf
DOI
10.1109/VLSIC.1993.920530
Filename
920530
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