Title :
16 Mbit synchronous DRAM with 125 Mbyte/sec data rate
Author :
Yunho Choi ; Myungho Kim ; Taejin Kim ; Seung-Hoon Lee ; Ho-Cheol Lee ; Churoo Park ; Siyeol Lee ; Cheol-Soo Kim ; Beornje Lee ; Sooin Cho ; Ejaz Haq ; Joel Karp ; Daeje Chin
Author_Institution :
Product Dev. Center, Samsung Electron. Co., Suwon, South Korea
Abstract :
The rapid increase in processor performance and memory density has created the need for high bandwidth DRAM for a variety of applications. A 3.3V 2M x8 synchronous DRAM is designed with a typical data rate of 125 Mbyte/sec using internal column address sequencing, pipelined 2 bit prefetch and variable output latching scheme. It supports operating frequencies up to 125 MHz.
Keywords :
CMOS integrated circuits; DRAM chips; pipeline processing; 125 MHz; 125 Mbyte/s; 16 Mbit; 3.3 V; dynamic RAM; high bandwidth DRAM; internal column address sequencing; pipelined 2 bit prefetch; synchronous DRAM; variable output latching scheme; CMOS integrated circuits, memory; DRAM chips; Pipeline processing;
Conference_Titel :
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIC.1993.920539
