Stand-by/active mode logic for sub-1 V 1 G/4 Gb DRAMs

Author

Takashima, D. ; Watanabe, S. ; Sakui, K. ; Nakano, H. ; Ohuchi, K.

Author_Institution

ULSI Res. Center, Toshiba Corp., Kawasaki, Japan

fYear

1993

fDate

19-21 May 1993

Firstpage

83

Lastpage

84

Abstract

A new stand-by/active mode Logic I,II has been developed for the future 1G/4Gb DRAMs. The proposed Logic I, II can achieve sub-1V supply voltage operation with small l /spl mu/A subthreshold leakage current during stand-by cycle, by allowance of 1 mA transistor leakage current during the active cycle. The gate delay of Logic I is reduced by 37%-30% with the optimized channel widths for Vcc=O.8-1.5 V, as compared with that of the conventional logic. The gate delay of Logic II is also reduced by 85%-40% as compared with that of the conventional logic at Vcc=0.8-1.5 V. The proposed Logic I.II are easily applicable not only to 1G/4Gb DRAMs but also other types of memories such as SRAM and battery-operated memories.

Keywords

DRAM chips; MOS integrated circuits; VLSI; integrated logic circuits; leakage currents; 1 Gbit; 1 to 1.5 V; 4 Gbit; DRAMs; SRAM; battery-operated memories; dynamic RAM; gate delay; stand-by/active mode logic; sub-1V supply voltage operation; subthreshold leakage current; transistor leakage current; DRAM chips; Logic-in-memory; MOS integrated circuits, memory; MOSFET logic devices; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920548

Filename

920548