Performance modeling of multiprocessors under correlated traffic

Author

Edirisooriya, Samantha ; Edirisooriya, Geetani

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

1992

fDate

12-15 Apr 1992

Firstpage

737

Abstract

A traffic model is proposed which does not assume the mutual independence of memory requests generated by the processors within a memory cycle, to evaluate performance in shared memory multiprocessors. The authors derive expressions for the bandwidth of crossbars and some shared bus networks. A traffic model is presented called the 2^N-ary symmetric traffic model to analyze the performance of multiprocessor systems in the presence of correlated traffic. Some numerical results are provided for both full and partial bus networks

Keywords

multiprocessor interconnection networks; performance evaluation; queueing theory; shared memory systems; 2^N-ary symmetric traffic model; correlated traffic; crossbars; memory cycle; memory requests; multiprocessor systems; mutual independence; numerical results; partial bus networks; shared bus networks; shared memory multiprocessors; traffic model; Bandwidth; Costs; Fault tolerance; Hardware; Multiprocessing systems; Multiprocessor interconnection networks; Performance analysis; Switches; Telecommunication traffic; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '92, Proceedings., IEEE

Conference_Location

Birmingham, AL

Print_ISBN

0-7803-0494-2

Type

conf

DOI

10.1109/SECON.1992.202426

Filename

202426