Title :
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory
Author :
Kobayashi, S. ; Nakai, H. ; Kunori, Y. ; Nakayama, T. ; Miyawaki, Y. ; Terada, Y. ; Onoda, H. ; Ajika, N. ; Hatanaka, M. ; Miyoshi, H. ; Yoshihara, T.
Author_Institution :
LSI Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time at low Vcc. A 4 Mb test device was fabricated in a 0.5 /spl mu/m CMOS triple well process and a typical access time of 90 ns was obtained at Vcc of 3 V.
Keywords :
CMOS integrated circuits; EPROM; convolutional codes; decoding; integrated memory circuits; 0.5 micron; 3 V; 3 V only sector erasable memory chip; 4 Mbit; 90 ns; CMOS triple well technology; DINOR flash memory; bit-by-bit programming control; compact source line driver; decoding scheme; hierarchical row decoder; high speed random access time; memory array architecture; threshold voltage detection circuit; threshold voltage distribution; CMOS integrated circuits, memory; Read-only memories; Threshold decoding;
Conference_Titel :
VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on
Conference_Location :
Kyoto, Japan
DOI :
10.1109/VLSIC.1993.920559
