High-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM

Author

Yabe, Tatsuro ; Matsuoka, F. ; Sato, Kiminori ; Hayakawa, S. ; Sato, Kiminori ; Matsui, Masaki ; Aono, A. ; Yoshimura, Hiroyuki ; Ishimaru, Kazuhisa ; Gojohbori ; Morita, S. ; Unno, Y. ; Kakumu ; Ochii, K.

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1993

fDate

19-21 May 1993

Firstpage

107

Lastpage

108

Abstract

This paper describes high-speed and low-standby-power circuit design of 1 to 5 V operating 1 Mb full CMOS SRAM. Several 1 V operating SRAMs have been reported so far, but none of them achieves both fast access time of 200 ns at 1 V and low standby power below O.1 /spl mu/W under 1-3 V range compatibly. This 1Mb SRAM is designed to achieve the performance above, which is suitable for both 1.5 V battery-operational application and 3 V use. Several circuit techniques such as Multi-Vth CMOS gates, Switched Delay-Line Pulse Generator ( SDLPG) and Resistor-inserted Current mirror sense Amplifier (RCSA) have been developed.

Keywords

CMOS integrated circuits; SRAM chips; 0.1 muW; 0.5 micron; 1 Mbit; 1 to 5 V; 200 ns; CMOS SRAM; battery-operational application; high-speed operation; low-standby-power circuit design; multi-Vth CMOS gates; resistor-inserted current mirror sense amplifier; static RAM; switched delay-line pulse generator; CMOS integrated circuits, memory; High-speed integrated circuits; SRAM chips;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1993. Digest of Technical Papers. 1993 Symposium on

Conference_Location

Kyoto, Japan

Type

conf

DOI

10.1109/VLSIC.1993.920564

Filename

920564