DocumentCode :
3070019
Title :
Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks
Author :
Morero, Damian A. ; Castrillon, M. Alejandro ; Ramos, Facundo A. ; Goette, Teodoro A. ; Agazzi, Oscar E. ; Hueda, Mario R.
Author_Institution :
Lab. de Comun. Digitales, Univ. Nac. de Cordoba, Cordoba, Argentina
fYear :
2011
fDate :
5-9 Dec. 2011
Firstpage :
1
Lastpage :
5
Abstract :
This paper presents a non-concatenated forward error correction (FEC) code suitable for applications in 100Gb/s optical transport networks (OTN). A typical requirement in this application is a net coding gain (NCG) >;10 dB at a bit error rate (BER) of 10-15 with an overhead (OH) of ~20%. As discussed in [1], non-concatenated codes are the ultimate frontier in terms of performance for OTN applications, because of their superior performance, lower latency, and lower overhead than concatenated codes. However, a major stumbling block for the use of these codes has been the existence of BER floors at levels significantly higher than the required 10-15(typically 10-10). In this paper we present a new coding scheme based on a low density parity check (LDPC) code with an expected net coding gain of 11.30dB at 10-15, 20% OH, and a block size of 24576 bits. This represents a significant improvement over the previous state of the art [2], based on a concatenated code with a block size of 74844 bits and 20.5% OH. The code is designed to minimize the BER floor while simultaneously reducing the memory requirements and the interconnection complexity of the iterative decoder [3]. Experimental results obtained with an FPGA-based hardware emulator demonstrate an NCG of 10.70 dB at a BER of 10-13and no error floors. These experimental results are extrapolated to 10-15 using importance sampling techniques, resulting in the expected performance stated above. Moreover, we find that fixed-point implementation is the main cause of error floors below 10-13Based on this finding, we introduce a new low complexity postprocessing technique to push BER floors down to 10-15.
Keywords :
communication complexity; concatenated codes; error statistics; field programmable gate arrays; forward error correction; optical fibre networks; parity check codes; BER floor; FPGA-based hardware emulator; OTN application; bit error rate; codeword length; fixed-point implementation; interconnection complexity; iterative decoder; low density parity check code; memory requirement; net coding gain; nonconcatenated FEC code; nonconcatenated forward error correction code; sampling technique; stumbling block; ultra-high speed optical transport network; Adaptive optics; Bit error rate; Complexity theory; Decoding; Encoding; Field programmable gate arrays; Parity check codes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Global Telecommunications Conference (GLOBECOM 2011), 2011 IEEE
Conference_Location :
Houston, TX, USA
ISSN :
1930-529X
Print_ISBN :
978-1-4244-9266-4
Electronic_ISBN :
1930-529X
Type :
conf
DOI :
10.1109/GLOCOM.2011.6133616
Filename :
6133616
Link To Document :
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