Title :
Current steering high-speed DAC: architecture analysis and simulation results
Author :
Choi, Yunyouiig ; Franco, Maloberti
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
A DAC architecture based on the current steering method is presented. The proposed architecture exploits the oversampling and uses a MASH like configuration. The DAC requires to use two current steering 5-bit D/A converters whose current references are properly scaled. The two output currents are summed at the output node to achieve the output signal. With an oversampling factor equal to 8 and 40 MHz band-width (clock frequency 640 MHz) it is possible to reach an SNR as large as 72 dB
Keywords :
circuit simulation; random noise; sampling methods; sigma-delta modulation; 40 MHz; 40 MHz bandwidth; 5-bit D/A converters; 640 MHz; 72 dB; 8 MHz; 8 MHz bandwidth; DAC architecture; MASH like configuration; SNR 72 dB; architecture analysis; clock frequency 640 MHz; current steering; oversampling; simulation; 3G mobile communication; Analytical models; Bandwidth; Base stations; Clocks; Delta-sigma modulation; Frequency; GSM; Multi-stage noise shaping; Noise shaping;
Conference_Titel :
Low Power/Low Voltage Mixed-Signal Circuits and Systems, 2001. (DCAS-01). Proceedings of the IEEE 2nd Dallas CAS Workshop on
Conference_Location :
Plano, TX
Print_ISBN :
0-7803-6624-7
DOI :
10.1109/DCAS.2001.920988
