Design framework for systolic-type arrays

We present a framework for the design and description of Systolic-type Arrays. The framework is based on the definition of a conceptual tool, Lines of Computation (LOC´s) that allows us to systematically define a generalization of the idea of Systolic Arrays and Wavefront Array Processors. We use three different architectures for parallel matrix multiplication to show the power of LOC´s to describe and generate Systolic-type Arrays. Finally, we present some topographical properties of Systolic Arrays that can be readily analyzed using LOC´s ideas.