Research and Design of Low Power Consumption Testing Generator for Integrated Circuits

Author

Wang, Yi

Author_Institution

Coll. of Phys. & Electron. Sci., Guizhou Normal Univ., Guiyang, China

Volume

4

fYear

2010

fDate

4-6 June 2010

Firstpage

340

Lastpage

343

Abstract

In this paper, Sources of power consumption for CMOS logical circuits are analyzed and several BIST technologies of low power consumption are summarized. In order to reduce the switching activity rate of internal nodes in circuit-under-test and raise the correlation between testing vector, the Random Single Input Change (RSIC)test theory is introduced. It can reduce the switching activity rate of nodes in the circuit-under-test to realize low power consumption during testing without lossing fault coverage, especially suitable for BIST of digital VLSI.

Keywords

CMOS digital integrated circuits; CMOS logic circuits; VLSI; built-in self test; power consumption; BIST technologies; CMOS logical circuits; circuit-under-test; digital VLSI; integrated circuits; power consumption; power consumption testing generator; random single input change test theory; testing vector; Built-in self-test; CMOS logic circuits; CMOS technology; Circuit analysis; Circuit testing; Energy consumption; Integrated circuit technology; Integrated circuit testing; Power generation; Switching circuits; Built-in-self-test; Integrated Circuit Testing; Low Power Consumption Testing; Testing Vector Generator; Vector Leap;

fLanguage

English

Publisher

ieee

Conference_Titel

Information and Computing (ICIC), 2010 Third International Conference on

Conference_Location

Wuxi, Jiang Su

Print_ISBN

978-1-4244-7081-5

Electronic_ISBN

978-1-4244-7082-2

Type

conf

DOI

10.1109/ICIC.2010.357

Filename

5513832