Optimization of Bank Switching Instructions in Embedded Systems through Static Analysis of Machine Codes

This paper describes a static machine code analyzer which helps to eliminate the redundant bank switching instructions in partitioned memory architectures. Our approach rests on a state transition diagram representing the memory bank switching corresponding to each bank selection instruction. Redundant data memory bank selection instructions in the intraprocedural sequence, loops and interprocedural routines in the application program are eliminated. Analysis is done at machine code levels, so no software or runtime overhead. This results in reduced code size as well as increased execution speed. No assertion or annotated assembly code is needed. This method scales well into large number of memory blocks as well as other architectures, once appropriate information is available. A prototype based on PIC 16F87X microcontrollers is described. A detailed algorithm is prescribed in this paper.