An ASIC library granular DRAM macro with built-in self test

System-on-a-chip architectures are generating increased interest as the level of integration is expanded by the arrival of 0.25 /spl mu/m processes. Many merged DRAM and logic applications use custom logic circuits that either surround or are embedded in a DRAM core. A more classic ASIC library approach where a DRAM macro family is used as a logic building block with the software tools associated with ASIC logic macros: i.e., timing analysis, place-and-route, logic simulation, and test generation. The macro operation is generic, yet versatile, allowing gate-array or standard-cell interface personalization. The design has a wide databit interface of 128 or 256 bits, separate databit-in and databit-out to ease bus contention, bit-write capability for multiplexing to narrower databit widths or partial databit-writes, and granular-density options from 0.5 Mb-8 Mb. Built-in self test (BIST) with two-dimensional redundancy calculation and allocation, along with in-situ burn-in capability, is also included. The DRAM macro design is architectured for reuse on future DRAM-generation sub-arrays and is adaptable to any number of address or databit-pin configurations. Its methodology and functionality have been verified in a 0.45 /spl mu/m trench DRAM technology.