500 Mb/s non-precharged data bus for high-speed DRAM

For a DRAM core with bandwidth per memory more than one order of magnitude higher than the current DRAMs without increasing the number of internal busses and the area and power they require, the data rate per DRAM must be increased. This nonprecharged bus combined with a bus amplifier that employs partial response detection (PRD) achieves 500Mb/s data-bus rate for read, 2.5 times larger than that of a conventional DRAM core. The isolated sense amplifier (ISSA) realizes more than 400 Mb/s data-bus data rate for write. Due to the intrinsic high data-rate of the bus, no core interleaves and no increase in the number of buses is needed to achieve the high-core bandwidth and high-data locality.