Effect of stacking chips and fluid/structure interaction simulation in 3D stacked flip-chip encapsulation process

In current study, simulation analysis was conducted to investigate the fluid/structure interaction (FSI) phenomenon in two, three, and four stacking chips package with through silicon via (TSV) during encapsulation process. In actual packaging, the visualization of FSI phenomenon is very hard due to the package size limitation, low availability of suitable equipment, and high experimental setup cost. Thus, modeling software such as FLUENT and ABAQUS were used to predict the fluid flow and structural deformation during the encapsulation process. Imitated package with scaled dimension were modeled using both finite volume and finite element code, coupled with MPCCI to perform the FSI analysis. The effects of increase in stacking chips number were investigated. All the three cases showed a similar mould filling rate using the designed inlet and outlet dimension. Moreover, void formation was also successfully reduced. Maximum von Mises stress and maximum displacement on perimeter of silicon chips and structure of TSV and solder bump were also determined. Larger chip displacement was observed at the edge compared to the corner of the chip. For two and four stacked chips package, the largest displacement of TSV and solder bumps structure occurred at the highest point of the structure while largest displacement occurred at the interface between the highest chip and its subsequent chip for three stacked chip package. The simulation model enhanced the understanding of FSI for stacked chip package during encapsulation process by providing better visualization and realistic prediction.