Design of low power non volatile SRAM cell using Magnetic Tunnel Junction

In this paper, we propose the design of a non-volatile SRAM which has low power dissipation. To design this SRAM, we use Magnetic Tunnel Junction as a storing element. MTJ comprises of two Ferro-magnetic layers separated by a dielectric tunnel barrier. One layer (fixed layer) has fixed magnetic field while that of second layer (free layer) can be altered. We use this property to realize an MTJ with the help of tanner tools. This realization has low power dissipation. Based on the magnetic states (parallel and anti-parallel fields), two resistances are formed in MTJ which differentiates the two logic states stored in MTJ. They are used to find the Tunneling Magneto Resistance Ratio (TMR). The two resistances that we attain in the simulation are 1.2KΩ and 300Ω. For the higher resistance we obtain the power dissipation as low as 50μW, while for the lower resistance we get 110μW. The TMR ratio obtained is 300%. Higher the TMR ratio, lower the resistance area.