A 255 Mb SDRAM with subthreshold leakage current suppression

Author

Hasegawa, M. ; Nakamura, M. ; Nanri, S. ; Ohkuma, S. ; Kawase, Y. ; Endoh, H. ; Miyatake, S. ; Akiba, T. ; Kawakita, K. ; Yoshida, M. ; Yamada, S. ; Sekiguchi, T. ; Asano, S. ; Tadaki, Y. ; Nagai, R. ; Miyaoka, S. ; Kajigaya, K. ; Horiguchi, M. ; Nakagome

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

1998

fDate

5-7 Feb. 1998

Firstpage

80

Lastpage

81

Abstract

A 204.9 mm/sup 2/ 256 Mb SDRAM has a 29 ns RAS access time and a 1ns clock access time. The SDRAM enables double-data-rate (DDR) at more than 300 Mb/s/pin, and features low-Vth and high-drivability MOSFETs combined with subthreshold leakage current suppression that reduces standby current to 200 /spl mu/A. A 64-cycle lock-in 0.1 ns resolution delay-locked-loop (DLL) is used.

Keywords

DRAM chips; MOS memory circuits; clocks; delay circuits; leakage currents; 256 Mbit; RAS access time; SDRAM; clock access time; delay-locked-loop; double-data-rate; high-drivability MOSFETs; standby current; subthreshold leakage current suppression; Circuits; Clocks; Delay; Immune system; Leakage current; MOS devices; MOSFETs; SDRAM; Substrates; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-4344-1

Type

conf

DOI

10.1109/ISSCC.1998.672384

Filename

672384