A study of insulated and passivated gate technology for InP FETs

Author

Lee, W. ; Iliadis, A. ; Martin, E. ; Mattingley, M.R. ; Aina, O.

Author_Institution

Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

fYear

1990

fDate

23-25 April 1990

Firstpage

282

Lastpage

290

Abstract

The effects of using a new surface passivation technique prior to PECVD SiO/sub 2/ deposition were studied, and the performance of the devices was correlated with the state of the interface at the gate electrode. Devices with gates made using the passivation only, passivation and subsequent SiO/sub 2/ deposition, and SiO/sub 2/ deposition without passivation were studied for a uniformly doped n-channel InP FET. The unpassivated SiO/sub 2/ insulated gates produced the lowest transconductance (g/sub m/) values: passivation prior to SiO/sub 2/ deposition improved the characteristics of the devices and increased g/sub m/ significantly. The passivated enhanced barrier gates produced the best characteristics and the highest transconductances consistently. In general the enhanced barrier gates demonstrated twice as high transconductance values as the SiO/sub 2/ insulated gates.<>

Keywords

III-V semiconductors; indium compounds; insulated gate field effect transistors; interface electron states; passivation; 10 kHz to 100 MHz; 135 mS; InP-SiO/sub 2/; PECVD; dynamic transconductance; enhanced barrier gates; interface state; n-channel FET; output conductance; passivated gate technology; surface passivation; transconductance; voltage gains; Chemical technology; Density measurement; Electrodes; FETs; Indium phosphide; Insulation; Interface states; Passivation; Thermal degradation; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Indium Phosphide and Related Materials, 1990. Second International Conference.

Conference_Location

Denver, CO, USA

Type

conf

DOI

10.1109/ICIPRM.1990.203032

Filename

203032