Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

This paper proposes a low power linear feedback shift register (LFSR) for test pattern generation (TPG) technique with reducing power dissipation during testing. The correlations between the consecutive patterns are higher during normal mode than during testing. The proposed approach uses the concept of reducing the transitions in the test pattern generated by conventional LFSR. The transition is reduced by increasing the correlation between the successive bits. The simulation result show that the interrupt controller benchmark circuit´s testing power is reduced by 46% with respect to the power consumed during the testing carried by conventional LFSR.