• DocumentCode
    3073011
  • Title

    Role of process gases in making tapered through-silicon vias for 3D MEMS packaging

  • Author

    Dixit, Pratima ; Vahanen, S. ; Salonen, Jarno ; Monnoyer, P.

  • Author_Institution
    3D Integration, VTT (Tech. Res. Center of Finland), Espoo, Finland
  • fYear
    2012
  • fDate
    24-26 Oct. 2012
  • Firstpage
    35
  • Lastpage
    38
  • Abstract
    This article report a continuous plasma etching process using SF6/O2/Ar gases for fabricating 100 μm deep tapered through-silicon vias (TSV). The flow rates of the process gases were changed to study their individual effect on the profile angle, via depth, sidewall roughness, and sideways undercut of the tapered vias. Tapered vias having profile angles varying from 70° to 85° and smooth sidewalls were etched by balancing the chemically-assisted isotropic etching of F* radicals, passivation film by O2, and ion-assisted passivation etching. The flow rates of SF6 and O2 were found to be the important factors which determine the profile angle and via surface roughness. After considering the individual effects of each gas, an optimized etching recipe was fixed, which was used to etch 100 μm deep vias having a profile angle of 83°. Insulation and seed layers were deposited by conventional low-temperature processes. The tapered vias were then partially filled by copper electrodeposition and redistribution lines were formed. The electrical resistance of tapered TSVs was measured to be between 3-8 mΩ for the majority of the TSVs.
  • Keywords
    argon; copper; electrodeposition; integrated circuit packaging; micromechanical devices; oxygen; sputter etching; sulphur compounds; surface roughness; three-dimensional integrated circuits; 3D MEMS packaging; F* radicals; SF6-O2-Ar; TSV; chemically-assisted isotropic etching; continuous plasma etching process; copper electrodeposition; electrical resistance; flow rates; insulation layers; ion-assisted passivation etching; low-temperature processes; passivation film; process gases; profile angle; redistribution lines; seed layers; sidewall roughness; sideways undercut; surface roughness; tapered through-silicon vias; tapered vias; via depth; Copper; Electrical resistance measurement; Etching; Plasmas; Resistance; Sulfur hexafluoride; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012 7th International
  • Conference_Location
    Taipei
  • ISSN
    2150-5934
  • Print_ISBN
    978-1-4673-1635-4
  • Electronic_ISBN
    2150-5934
  • Type

    conf

  • DOI
    10.1109/IMPACT.2012.6420230
  • Filename
    6420230