Title :
Massively Deployable Intelligent Sensors for the Smart Power Grid
Author :
Jain, Vijay K. ; Chapman, Glenn H.
Author_Institution :
Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
This paper investigates a fault tolerant “3-D Heterogeneous Sensor System on a Chip (HSoC)” for meeting the challenges of distributed power grid monitoring, fault detection, and control. In the past, the management of the power system, including detection of power grid faults, their location, and load-sharing has been carried out largely by remote central stations, which has often incurred delays and very costly domino effects. A possible new solution is to use a matrix of distributed fault tolerant sensors that can sense deviations as well as take local actions. A sensing and computing architecture is presented and the issues of defect and fault tolerance, at multiple levels - intra-chip, sensor system, and power system level, are addressed. First we describe the intra chip level fault tolerance which allows the fabrication of 3D devices integrating magnetic field sensors to detect transmission line currents, and on chip processing. Next at the sensor matrix level the system must deal with chip failures and soft errors due to the harsh environment. Therefore the paper focuses on the sensor matrix required for detection of transmission line fault detection and the corresponding distance estimation. In particular, the use of multiple devices at-D-x, -x, D-x, and 2D-x diminishes the probability of loss of detection considerably while simultaneously enhancing the accuracy of fault distance estimates.
Keywords :
distributed power generation; intelligent sensors; smart power grids; 3D heterogeneous sensor system; deployable intelligent sensor; distributed power grid monitoring; fault detection; power grid fault; sensor matrix; smart power grid; transmission line fault detection; Computer architecture; Fault tolerance; Fault tolerant systems; Microprocessors; Power grids; Sensor systems; 3D heterogenous sensor; Fault tolerance; power grid fault detection; senor matrix;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4244-8447-8
DOI :
10.1109/DFT.2010.46