The DTWP : An LPC based dynamic time warping processor for isolated word recognition

Special purpose hardware for calculating dynamic time warp distances has been designed and tested utilizing TTL technology. The "Dynamic Time Warp Processor" (DTWP) performs all of the necessary arithmetic and decision making operations for selecting a word from a given vocabulary based on log likelihood distance measurements. The speed limitation in previously designed hardware was due to programmed decision making (often referred to as combinatorics). The combinatorics have been implemented in hardware in such a way that the decisions are made in the time of several gate delays rather than the time of several program cycles. Thus, a dynamic time warp (DTW) is performed on typical 40 frame templates in less than one millisecond. The DTWP serves as a slave to a 16-bit microcomputer. It performs all of the computation and control necessary for pattern classification. A board level implementation is now operational. VLSI implementation of the processor is currently in progress. All logic has been designed in 2.5µm CMOS polycells and has been simulated on the MOTIS timing simulator. The timing simulations indicate that the DTW time of 1 msec implemented at the board level can also be met on the integrated circuit.