A Study of eSRAM Testability

Summary form only givenIn the market, consumers demand high performance, high quality, low power, low cost as well as increased functionality for VLSI. Scaling is the key factor for satisfying with these demands. Consumers also require realizing all of demands in as short development term as possible. VLSI venders, on the other hand, struggle with a lot of problems, such as prolonging development term, rising development cost, degrading quality, increasing test cost, and low yield. As scaling proceeding, we have to care about not only functional failures caused by macroscopic visible particles, but also parametric variations caused by atomic particles which has not been concerned with before. In addition, transistor variation caused by do pant fluctuations or surface roughness considerably affects a VLSI yield. Especially, eSRAM reveals unique failure modes that cannot be seen in logic circuits, because eSRAM is more susceptible to the variations than logic circuits. Increasing volume of eSRAM escalates the problem of low yield of VLSI. In contrast, taking an advantage of array structure in circuit and layout of eSRAM, we are able to identify locations and causes of the failures through a test sequence diagnosing the eSRAM failure modes. Information obtained from the test can be fed back to a fabrication process to decrease the failures. This feedback refines overall VLSI quality not only in eSRAM, but also in the other circuits, such as logic circuits and I/O. In this talk, I show firstly VLSI progress in the view of eSRAM. Next, I explain yield problems of today´s VLSI. Then, I describe the problems caused by increasing volume of eSRAM, the unique failure mode of eSRAM, and solutions for them. I discuss an important role of eSRAM to build up and maintain a VLSI fabrication line. Finally, I talk some hot topics about VLSI testing with eSRAM.