Title :
Assembly and reliability assessment of 50µm-thick chip stacking by wafer-level underfill film
Author :
Kuo-Shu Kao ; Ren-Shin Cheng ; Chau-Jie Zhan ; Jing-Yao Chang ; Tsung-Fu Yang ; Shin-Yi Huang ; Chia-Wen Fan ; Su-Mei Chen ; Su-Ching Chung ; Yu-lan Lu ; Mei-Lun Wu ; Tai-Hung Chen
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
In order to meet the demands of high-performance, high-speed, small form factor and multi-function integration in portable electronic products, the development of packaging technology now trends toward system-in-package (SiP) technology. Three-dimension (3D) integrated circuit technology provides a way to integrate complex micro systems through vertical interconnections among individual devices/chips. For the multi-chip stacking with fine gap and fine pitch solder micro bump interconnection, the dispensing of capillary underfill presents a major limitation in term of process time and process ability during assembly process. In this study, for realizing the multi-chip stacking, we developed a simplified assembly process by wafer-level underfill (WLUF). The WLUF film was laminated on 8” chip wafer with a thickness of 50μm. The chosen solder micro bump structure was Cu/Ni/Sn2.5Ag with a pitch of 30μm. After wafer dicing, the chip with WLUF was assembled on the substrate chip having the same micro bump structure. The optimized bonding parameters in such assembly process were also determined. The experimental results revealed that a robust joining and no voids formed between bonding interface could be achieved by this simplified assembly process. The results of reliability test showed that all samples could pass LV-3 pre-condition test. The failure percentage was about 10% under 1000 cycles of TCT where the failure mode was the cracks of micro joints and Al pad. The failure percentage was about 52% under 1000 hours of THST where the failure mode was crack of micro joints. All samples could pass the Un-biased HAST test. We also evaluated the feasibility of multi-thin-chip stacking by WLUF film. The experimental results showed that the first-layer micro joints raised 2% increase in contact resistance and the thickness of IMC layer increased 1μm thick only after four-layer chip stacking process. These experimental results displayed that the - LUF material exhibited a highly applied potential for multi-chip assembly process.
Keywords :
assembling; bonding processes; contact resistance; fine-pitch technology; integrated circuit interconnections; integrated circuit reliability; system-in-package; three-dimensional integrated circuits; Cu-Ni-SnAg; LV-3 pre-condition test; WLUF film; assembly assessment; bonding interface; capillary underfill; complex microsystems; contact resistance; failure mode; failure percentage; fine pitch solder microbump interconnection; form factor; microbump structure; multichip assembly process; multichip stacking; multifunction integration; multithin-chip stacking; optimized bonding parameters; packaging technology; portable electronic products; process ability; process time; reliability assessment; size 30 mum; size 50 mum; size 8 in; substrate chip; system-in-package technology; three-dimension integrated circuit technology; time 1000 hour; un-biased HAST test; vertical interconnections; wafer dicing; wafer-level underfill film; Assembly; Bonding; Films; Joints; Reliability; Stacking;
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2012 7th International
Conference_Location :
Taipei
Print_ISBN :
978-1-4673-1635-4
Electronic_ISBN :
2150-5934
DOI :
10.1109/IMPACT.2012.6420249