Warning Prediction Sequential for Transient Error Prevention

Error Detection Sequential (EDS) is gaining enormous importance in timing error detection. In this work, we propose a warning detection scheme for sequential circuits which is very useful for dynamic, transient error prevention. The circuit consists of data edge detector, warning window generator and warning detector along with traditional Flip-flop. The delayed data is monitored during the warning window to flag a warning signal before the data enters the erroneous zone. We also propose an area efficient edge detector which reduces the area of the proposed FF substantially. The proposed circuit can be used in Dynamic Voltage Scaling (DVS) for low power application and helps in determining when to stop further reduction in supply voltage. It is also useful in avoiding delay degradation due to aging. The feasibility of the circuit is simulated in industrial 65 nm technology node.