90 nm node damascene copper stress voiding model and lifetime extrapolation methodology

Stress induced by thermal expansion mismatch between metal, silicon substrate and dielectrics may affect the integrity of copper interconnects. As a matter of fact, the voids formed by vacancy coalescence beneath vias, are likely to induce opens in the interconnects. With a view to predict the lifetime of copper interconnects, we developed a predictive model of the resistance evolution due to stress induced voiding. This model is validated by experimental investigation of the resistance evolution in time of different types of via chains during isothermal annealing lasting up to 1000 h. This model is able to simulate resistance increase depending on the temperature and geometry. Thus, it is possible to optimize test structures and to evaluate effective acceleration factors.