Micro bridge technology for 3D-IC interconnection could benefit the 3D-IC test strategy

Performing electrical test is the most challenge process in the 3D-IC device fabrication and manufacturing. There have been many papers published and presented for 3D-IC device testing technology such as 3D-IC design for test, test for less in the 3D-IC manufacturing etc... Most of them are circuit design related techniques. In this paper we will discuss a different point of view in the device packaging technologies that may affect the cost of testing. The main technologies for integrating and fabricating the 3D-IC device and system are (1) Through Silicon Via (TSV) technology for vertical communication; (2) interconnecting technology to accomplish the up and down signal flow between wafer layers and (3) stacking technology to complete the final assembly of the 3D-IC device and system. One very important step in the integration and manufacturing process is the testing and evaluating of the 3D-IC stacked system. This paper will dedicate to the issue of choosing the right interconnecting technology for cost effective consideration by introducing the Micro Bridge Technology. With the right choice of interconnecting technology, we will be benefited from the reduction of the 3D-IC system integration and testing through both cost and complexity.