Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging

The unstable/unpredictable LSI operation caused by the PVT (Process Voltage Parameter) variations, along with the aging effect such as NBTI/PBTI, is one of the serious issues in current and future scaled LSIs. In these situations, where operation environments in the field are hard to predict at the stages of circuit design and test, the conventional approach of the margin-based design and test in the synchronous architecture has to pay a large amount of penalty in operation speed in order to guarantee the safe operation. Especially from a view point of the delay fault, the unpredictable variation is expected to be worse in future by the ΓΓRS report. This presentation shows recent results of self-synchronous circuits studied in our research group. The circuits are designed to be resilient for PVT variations and the aging effect without paying so much speed penalty. In order to mitigate the margin penalty, several kinds of pseudo-synchronous approaches have been proposed recently, where circuits have error avoidance/recovery mechanisms along with delay-fault detection/prediction functions mainly by means of multiple clocking to check delay margin-to-fault at real time operation, instead of design stage. In cases of error detections, the circuits have to have mechanisms to roll back and retry the erroneous operations. In cases of error predictions, the circuits have to have mechanisms to avoid the predicted faults by such ways as clock re-timing/borrowing. These approaches, however, still need to assume a finite timing margin/window, in which all the delay variation should be confined, otherwise resulting in detection/prediction failures. As the scaling of LSI proceeds, the magnitude of the timing variation due to PVT variations is considered to be quite large, so that a large portion of the clock period would be occupied by this timing window for the fault detection/prediction. Thus we have to pay a penalty in operation speed again even in the pseudo-s- - ynchronous approaches. As a candidate of the final solutions for PVT-safe and adaptive circuits, we are studying self-synchronous circuits. The circuits have a completion-detection mechanism for safe and adaptive clocking and are ideally delay-fault free. The dual-rail logic used in our study is a promising candidate to realize the required mechanism, where the delay variations cause no delay-fault without so much penalty of operation speed, though a time spent for the completion detection is a new penalty. They are adaptive for PVT variations for the minimal speed degradation. The operation speed is determined by average delay of logic, not by the worst delay. The dual-rail logic gives us another feature to detect logic faults (permanent and intermittent) due to its redundant logic coding. Large PVT variations finally cause logic faults, even though our approach is delay-fault free. A mechanism for the logic fault detection (and recovery) is essential for such approaches like us to realize dependable operation. If a delay-fault free circuit has no logic-error detection mechanism, it would be hard to guarantee the correct operation under severe environments in terms of voltage temperature variation. In this presentation we first show the fundamental architecture of our self-synchronous circuits. Then we show a preliminary result of resilient and adaptive features of the self-synchronous circuits. Finally we demonstrate an experimentally developed SSFPGA (SelfSynchronous FPGA) as an application of the self-synchronous approach. We chose FPGA as an example for demonstration because of it re-configurability. The yield loss or imperfect fabrication would also be one of important issues in future scaled LSI. As integration density on a chip is approaching that of neurons in a human brain, the perfect reproducibility of the LSI might be no more expected. The reconfigurability or programmability would be a key feature not only in human beings but also in future LSI. The