The application of pad adhesion for the validation of halogen free pad cratering concern

The conversion to lead free and halogen free materials have raised several new assembly and reliability issues. The reliability concern attaches gradually more importance to the pad cratering on Printed Circuit Boards (PCBs). The cracking happened on the laminate under the solder connect pads, known as pad craters, is the board level reliability issue related to mechanical stresses. We will establish a mechanistic understanding of pad cratering through the use of joint level testing techniques in this study. The occurrence of pad cratering varies under the given mechanical stress in different factors, including, the size, construction and surface finish of the BGA, solder alloy, and solder mask design, pad size, material and surface finish of the PCBs. The board level bend, and drop tests can be used to determine in the JESD Standard if the entire environment can survive after mechanical stress without having any failures. In this paper, it will be investigated the pad adhesion of board material and pad size on the joint level test for the failure mode of pad cratering. This study focuses to establish a mechanistic understanding of pad cratering through the use of joint-level testing techniques that are cold ball pull. Both pad cratering and mechanical stress lifetimes are taken into consideration, and the results indicate that these two modes are not correlated. The individual pad cratering is found to differ with laminate material, glass style, and micro-via. If we can find that the relationship between joint-level testing is compared to the performance in board level mechanical stresses test. Here we see that joint level testing is far more general, in terms of qualifying the robustness of the laminate. For this reason, how to correlate the pad adhesion and performance of board level mechanical stresses test as the next step in order to find the relationship between the adhesion force for the pad cratering and life time of board level mechanical test so as to op- imize the performance of PCB design.