Procedure for quantitative fWLR monitoring of gate dielectric reliability

A fast wafer level reliability (fWLR) stress method for quantitative gate dielectric reliability monitoring is introduced. It is essentially a highly accelerated constant voltage stress. The challenges of the method are fast measurement capability for good time resolution and the reliable breakdown detection during stress. The derivation of the in-line monitoring parameter and the reliability limit for a control card are described in detail. It is necessary to generate a small voltage acceleration data base for derivation of the reliability limit. An example of such a data base and measurement results of the critical monitoring parameter are presented. The defect density can be determined from the charge to breakdown that is simultaneously acquired. For better resolution, charge to breakdown from both a pre-stress voltage ramp and the constant voltage test are combined.