Reliability-Driven System-Level Synthesis of Embedded Systems

This paper proposes an enhanced system-level synthesis flow for the design of reliable embedded systems, extending the classical process to introduce fault mitigation properties in the design under consideration. The strategy first explores the adoption of hardening techniques that, given the initial task graph and the user´s reliability requirements, introduce redundancies and mapping constraints on the available resources, which possibly expose fault detection/tolerance features. The reliability-aware task graph is then implemented by means of a classical mapping and scheduling approach thus obtaining the hardened implementation. Experimental results are reported to support the validity of the proposal.