Title :
VLSI neural network with digital weights and analog multipliers
Author :
Koosh, Vincent E. ; Goodman, Rodney
Author_Institution :
California Inst. of Technol., Pasadena, CA, USA
Abstract :
A VLSI feedforward neural network is presented that makes use of digital weights and analog multipliers. The network is trained in a chip-in-loop fashion with a host computer implementing the training algorithm. The chip uses a serial digital weight bus implemented by a long shift register to input the weights. The inputs and outputs of the network are provided directly at pins on the chip. The training algorithm used is a parallel weight perturbation technique. Training results are shown for a 2 input, 1 output network trained with an AND function, and for a 2 input, 2 hidden unit, I output network trained with an XOR function
Keywords :
CMOS analogue integrated circuits; VLSI; analogue multipliers; feedforward neural nets; gradient methods; learning (artificial intelligence); neural chips; parallel algorithms; perturbation techniques; AND function; CMOS process; VLSI feedforward neural network; XOR function; analog multipliers; chip-in-loop training algorithm; current source circuit; digital weights; gradient descent; long shift register; neuron circuit; parallel weight perturbation technique; serial bus; synapse; Analog computers; Computer networks; Counting circuits; Feedforward neural networks; Hardware; Neural networks; Pins; Shift registers; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-6685-9
DOI :
10.1109/ISCAS.2001.921290
