Architecture for a VLSI implementation of an LPC-based, isolated-word recognition system

An architecture for a general-purpose, programmable LPC-based speech processing hardware system has been designed. In this paper, we present the VLSI architecture for two custom-designed microprocessors in an isolated-word recognition task. A recognition simulation yielded an average error rate of under 1.5% on a medium-size vocabulary with a partially confusable lexicon. The hardware performance is in close agreement with the simulation results. Due to efficient hardware architecture and algorithms, all signal analysis can be done in about 30% real-time with medium-speed multiplication. Since the custom microprocessors were designed for VLSI implementation, it is expected that the total system cost can reach well below $100.00, and occupy under 16 square inches of board space.