Identifying the sources of unpredictability in COTS-based multicore systems

COTS-based multicores are now the preferred choice for hosting embedded applications owing to their immense computational capabilities, small form factor and low power consumption. Many of these embedded applications have real-time requirements and real-time system designers must be able assess them for their predictability and provide guarantees (at design time) that they deliver the correct functional behavior within predefined time bounds. However, the underlying architecture of commercially available multicores is extremely complex and non-amenable to straight-forward timing analysis. In this paper, we highlight the architectural features leading to temporal unpredictability, which mainly involve shared hardware resources, such as buses, caches, and memories. We explore some of the existing work in timing analysis with respect to these features, identify their limitations, and present some unaddressed issues that must be dealt with to ensure safe deployment of real-time systems.