Design and Implementation of Reconfigurable Security Hash Algorithms Based on FPGA

Today, security is a topic which attacks the great interest of researchers. Many encryption algorithms have been investigated, and developed in the last years. Hash functions are important security primitives used for authentication and data integrity. The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. It can implement many different cipher algorithms flexibly and quickly, and be used in many fields. This work is related to hash functions FPGA implementation. Five different hash functions SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 are studied. A reconfigurable architecture is proposed for the implementation of all of them in the same hardware module. Finally, it gives the implementation results based on the FPGA of the family of Stratix II of Altera Corporation. The proposed system reaches throughput values equal to 727.853 Mbps for SHA-1, 909.816 Mbps for SHA- 224/256, and 1.456 Gbps for SHA-384/512 respectively.