Digital background calibration of a 10 b 40 M sample/s parallel pipelined ADC

This time-interleaved pipelined ADC uses monolithic digital background calibration to overcome the effects of the offset and gain mismatches between channels. The contributions here are use of digital background calibration to overcome these mismatches and implementation of these techniques in conjunction with the ADCs on one CMOS IC. Background calibration is done by adding a calibration signal to the ADC input and processing both simultaneously. A potential advantage of this approach is that the calibration signal acts as dither and improves the linearity of the system.