8 b 75 M sample/s 70 mW parallel pipelined ADC incorporating double sampling

This 8b pipelined analog-to-digital converter (ADC) incorporates double sampling into the residue signal path of a 1.5b-per-stage architecture to effectively double the throughput of the ADC for a given analog power consumption. Residue amplifiers and sub-ADC comparators are shared between two time-interleaved channels and the sampling capacitors in the second stage are scaled in order to reduce power consumption. The ADC presented here achieves 75 MSamples/s while consuming 70 mW. The converter measures 5.5 mm/sup 2/ and is fabricated in a 3.3 V 0.5 /spl mu/m digital CMOS process with four levels of metal and no special mask layers for passive components.